Why do AI chips depend on TSMC and Taiwan?

Chip design and chip manufacturing are separate businesses. Nvidia and AMD are "fabless": they draw the chip, then pay a foundry to make it. A foundry is a contract factory for semiconductors, and a modern one costs many billions of dollars to build. TSMC, founded in 1987, pioneered that model and describes itself as the world's leading dedicated foundry.

The dependence is stated plainly in filings. AMD's latest quarterly report says it relies on TSMC for all its microprocessor and GPU wafers at 7 nanometres or smaller. Nvidia's annual report names TSMC and Samsung as its foundries and says its supply chain is mainly concentrated in Asia, adding that its business depends on reliable supply from partners, especially in Taiwan and South Korea.

How an AI chip gets made

Step	What happens	Who does it, in a typical case
Design	Engineers lay out the chip	Nvidia, AMD, Google, Broadcom
Wafer	The chips are printed on a silicon disc	TSMC
Memory	Stacks of fast memory are made separately	SK hynix, Micron, Samsung
Advanced packaging	Processor and memory are bonded side by side	TSMC's CoWoS, and others
Assembly	Chips go onto boards and into racks	Foxconn (Hon Hai), Wistron and others

Packaging is the step beginners tend to miss. CoWoS is TSMC's method for placing a large processor and its memory on one shared base, so they can exchange data at very high speed. Nvidia's filing names CoWoS directly. On TSMC's October call, its chief executive said CoWoS is still its customers' first choice, while acknowledging that competitors offer serious alternatives.

The numbers from TSMC's latest quarter

TSMC reported its third quarter of 2026 on October 15.

Measure	Figure
Revenue	$46.72 billion, up 41.2% from a year earlier
Gross margin	66.4%
Share of revenue from high-performance computing (mostly AI and data-centre chips)	68%
Share of wafer revenue from 7 nm or better	79% (2 nm 8%, 3 nm 33%, 5 nm 28%, 7 nm 10%)
Planned capital spending for 2026	$60 billion to $64 billion

A "nanometre" label such as 3 nm is now mostly a generation name, not a physical measurement. Newer generations generally fit more transistors in the same space and use less energy per calculation, which matters when electricity limits a data centre.

Asked about demand, C.C. Wei, TSMC's chief executive, said the gap between demand and supply was still quite big. The company had earlier guided to AI accelerator revenue growing at a mid- to high-50s percentage each year from 2024 to 2029, and he declined to set a new figure beyond saying demand was very robust. TSMC also says it now sends its own teams to check on US data centre construction and power supply, a sign it does not simply take customers' forecasts at face value.

Where the factories are going

On the same call, TSMC described nearly 20 new plants in progress. Its plan is the clearest evidence of where the centre of gravity stays:

Location	What TSMC said in October 2026
Taiwan	13 leading-edge and advanced packaging plants over the next several years; 2 nm ramping at Hsinchu and Kaohsiung
Overseas in total	Five to six plants
Arizona	Second plant built, tools moving in, volume production in the third quarter of 2027
Japan	Second plant to use 3 nm, volume production in 2028
Texas	Teams evaluating sites for more US capacity; talks continuing

Why this worries governments

Taiwan's status is contested. Beijing claims the island, and a blockade, a conflict or even a long disruption would hit the supply of the advanced chips described above, and not only those used for AI. Nobody can price that risk with confidence, and this article does not try to. Ordinary hazards count too: AMD's filing lists natural disasters such as earthquakes and tropical cyclones among its risks. For a country like Canada, this means even a fully domestic data centre, built under a sovereign compute plan, usually runs on chips from this same chain.

Try it: Pick any AI chip in the news and trace it through the table above. Look in the maker's latest annual report for the word "foundry" and for "Taiwan". You will usually find the dependence described in the company's own risk section.

Would building factories elsewhere remove the Taiwan risk?

It would reduce the risk, not remove it, at least on the timelines now public. By TSMC's own count, Taiwan gets more than twice as many new plants as the rest of the world combined. Its newest process in volume, 2 nm, is ramping at the two Taiwan sites, while the Japan plant named above targets 3 nm in 2028 and the second Arizona plant reaches volume production only in late 2027.

Cost is the other limit. TSMC says that overseas plants cost more to run and expects them to cut its gross margin by 3% to 4% over the coming years. Someone ends up paying for that resilience, whether through chip prices, lower margins or government subsidies.

And a chip is more than a wafer. If a wafer printed in Arizona still needs advanced packaging, and memory from South Korea, the supply chain still crosses the Pacific. That is why the useful question for a buyer or a policymaker is not "is it made in America?" but "which steps, in which places, and what happens if one stops?"